december 2009 i ? 2009 actel corporation see the actel website for the latest version of the datasheet. v5.9 proasic plus ? flash family fpgas features and benefits high capacity commercial and industrial ? 75,000 to 1 million system gates ? 27 k to 198 kbits of two-port sram ? 66 to 712 user i/os military ? 300, 000 to 1 million system gates ? 72 k to 198 kbits of two port sram ? 158 to 712 user i/os reprogrammable fl ash technology ? 0.22 m 4 lm flash-based cmos process ? live at power-up (lapu) level 0 support ? single-chip solution ? no configuration device required ? retains programmed design during power-down/up cycles ? mil/aero devices operate over full military temperature range performance ? 3.3 v, 32-bit pci, up to 50 mhz (33 mhz over military temperature) ? two integrated plls ? external system performance up to 150 mhz secure programming ? the industry?s most effective security key (flashlock ? ) low power ? low impedance flash switches ? segmented hierarchical routing structure ? small, efficient, configurable (combinatorial or sequential) logic cells high performance routing hierarchy ? ultra-fast local and long-line network ? high-speed very long-line network ? high-performance, low skew, splittable global network ? 100% routability and utilization i/o ? schmitt-trigger option on every input ? 2.5 v / 3.3 v support with individually-selectable voltage and slew rate ? bidirectional global i/os ? compliance with pci spec ification revision 2.2 ? boundary-scan test ieee std. 1149.1 (jtag) compliant ? pin-compatible packages across the proasic plus family unique clock condi tioning circuitry ? pll with flexible phase, multiply/divide, and delay capabilities ? internal and/or external dynamic pll configuration ? two lvpecl differential pa irs for clock or data inputs standard fpga and asic design flow ? flexibility with choice of in dustry-standard front-end tools ? efficient design through front-end timing and gate optimization isp support ? in-system programming (isp) via jtag port srams and fifos ? smartgen netlist generation ensures optimal usage of embedded memory blocks ? 24 sram and fifo configurations with synchronous and asynchronous operation up to 150 mhz (typical) table 1 ? proasic plus product profile device apa075 apa150 apa300 1 apa450 apa600 1 apa750 apa1000 1 maximum system gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 tiles (registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 embedded ram bits (k=1,024 bits) 27 k 36k 72 k 108 k 126 k 144 k 198 k embedded ram blocks (256x9) 12 16 32 48 56 64 88 lvpecl 222 2 2 2 2 pll 222 2 2 2 2 global networks 4 4 4 4 4 4 4 maximum clocks 24 32 32 48 56 64 88 maximum user i/os 158 242 290 344 454 562 712 jtag isp yes yes yes yes yes yes yes pci yes yes yes yes yes yes yes package (by pin count) tqfp 100, 144 100 ? ? ? ? ? pqfp 208 208 208 208 208 208 208 pbga ? 456 456 456 456 456 456 fbga 144 144, 256 144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152 cqfp 2 208, 352 208, 352 208, 352 ccga/lga 2 624 624 notes: 1. available as commerci al/industrial and military/mil-std-883b devices. 2. these packages are available only for military/mil-std-883b devices. v5.9 ?
proasic plus flash family fpgas ii v5.9 ordering information apa1000 fg _ part number speed grade blank = standard speed package type pq = plastic quad flat pack (0.5 mm pitch) tq = thin quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) bg = plastic ball grid array (1.27 mm pitch) cq = ceramic quad flat pack (1.05 mm pitch) cg = ceramic column grid array (1.27 mm pitch) lg = land grid array (1.27 mm pitch) 1152 i package lead count application (ambient temperature range) g lead-free packaging blank = standard packaging g = rohs compliant packaging blank = commercial (0c to +70c) i = industrial (?40c to +85c) pp = pre-production es = engineering silicon (room temperature only) m = military (?55c to 125c) b = mil-std-883 class b 150,000 equivalent system gates apa150 = 75,000 equivalent system gates apa075 = apa300 300,000 equivalent system gates = apa450 450,000 equivalent system gates = apa600 600,000 equivalent system gates = apa750 750,000 equivalent system gates = apa1000 1,000,000 equivalent system gates =
proasic plus flash family fpgas v5.9 iii device resources general guideline maximum performance numbers in this datasheet are based on characterized data. actel does not guarantee performance beyond the limits sp ecified within the datasheet. user i/os 2 commercial/industrial military/mil-std-883b device tqfp 3 100-pin tqfp 3 144-pin pqfp 3 208-pin pbga 3 456-pin fbga 3 144-pin fbga 3 256-pin fbga 3 484-pin fbga 3 676-pin fbga 3 896-pin fbga 3 1152-pin cqfp 208-pin cqfp 352-pin ccga/ lga 624-pin apa075 66 107 158 100 apa150 66 158 242 100 186 4 apa300 158 5 290 5 100 5 186 4, 5 158 248 apa450 158 344 100 186 4 344 4 apa600 158 5 356 5 186 4, 5 370 4 454 158 248 440 apa750 158 356 454 562 6 apa1000 158 5 356 5 642 5, 6 712 6 158 248 440 notes: 1. package definitions: tqfp = thin quad flat pack, pqfp = plastic quad flat pack, pbga = plastic ball grid array, fbga = fine p itch ball grid array, cqfp = ceramic quad flat pack, ccga = ce ramic column grid array, lga = land grid array 2. each pair of pecl i/os is counted as one user i/o. 3. available in rohs compatible packages. ordering code is "g." 4. fg256 and fg484 are footprint-compatible packages. 5. military temperature plastic package offering 6. fg896 and fg1152 are footprint-compatible packages.
proasic plus flash family fpgas iv v5.9 temperature grade offerings speed grade and temperature matrix package apa075 apa150 apa300 apa450 apa600 apa750 apa1000 tq100 c, i c, i tq144 c, i pq208 c, i c, i c, i, m c, i c, i, m c, i c, i, m bg456 c, i c, i, m c, i c, i, m c, i c, i, m fg144 c, i c, i c, i, m c, i fg256 c, i c, i, m c, i c, i, m fg484 c, i c, i, m fg676 c, i, m c, i fg896 c, i c, i, m fg1152 c, i cq208 m, b m, b m, b cq352 m, b m, b m, b cg624 m, b m, b note: c = commercial i = industrial m = military b = mil-std-883 std. c ? i ? m, b ? note: c = commercial i = industrial m = military b = mil-std-883
proasic plus flash family fpgas v5.9 1-1 device family overview the proasic plus family of devices, actel?s second- generation family of flash fpgas, offers enhanced performance over actel?s proa sic family. it combines the advantages of asics with the benefits of programmable devices through nonvolatile flash technology. this enables engineers to create high-density systems using existing asic or fpga design flows and tools. in addition, the proasic plus family offers a unique clock conditioning circuit based on two on-board phase-locked loops (plls). the family offers up to one million system gates, supported with up to 198 kbit s of two-port sram and up to 712 user i/os, all providing 50 mhz pci performance. advantages to the de signer extend beyond performance. unlike sram-bas ed fpgas, four levels of routing hierarchy simplify routing, while the use of flash technology allows all functionality to be live at power- up. no external boot prom is required to support device programming. while on-board security mechanisms prevent access to th e program information, reprogramming can be performed in-system to support future design iterations and field upgrades. the device?s architecture mitigates the complexity of asic migration at higher user volume . this makes proasic plus a cost- effective solution for applic ations in the networking, communications, computing, and avionics markets. the proasic plus family achieves its nonvolatility and reprogrammability through an advanced flash-based 0.22 m lvcmos process with four layers of metal. standard cmos design techniques are used to implement logic and control functions, including the plls and lvpecl inputs. this results in predictable performance compatible with gate arrays. the proasic plus architecture provides granularity comparable to gate arrays. th e device core consists of a sea-of-tiles ? . each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropri ate flash switches. the combination of fine granul arity, flexible routing resources, and abundant flash switches allows 100% utilization and over 95% routability for highly congested designs. tiles and larger functions are interconnected through a four-level routing hierarchy. embedded two-port sram blocks with built-in fifo/ram control logic can have user-defined depths and widths. users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. the unique clock conditioning circuitry in each device includes two clock conditioning blocks. each block provides a pll core, delay lines, phase shifts (0 and 180 ), and clock multipliers/d ividers, as well as the circuitry needed to provide bidirectional access to the pll. the pll block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. the clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). the pll can be configured internally or externally during operation without redesigning or reprogramming the part. in addition to the pll, there are two lvpecl differential input pairs to accommodate high-speed clock and data inputs. to support customer needs for more comprehensive, lower-cost, board-level testing, actel?s proasic plus devices are fully compatible with ieee standard 1149.1 for test access port and boundary-scan test architecture. for more information concerning the flash fpga implementation, please refer to the "boundary scan (jtag)" section on page 2-8 . proasic plus devices are available in a variety of high- performance plastic packages . those packages and the performance features discussed above are described in more detail in the following sections.
proasic plus flash family fpgas 1-2 v5.9 proasic plus architecture the proprietary proasic plus architecture provides granularity comparable to gate arrays. the proasic plus device core consists of a sea-of-tiles ( figure 1-1 ). each tile can be conf igured as a three-input logic function (e.g., nand gate, d-flip-flop, etc.) by programming the appropriate flash switch interconnections ( figure 1-2 and figure 1-3 on page 1-3 ). tiles and larger functions ar e connected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. flash switches are programmed to connect signal lines to the appropriate logic cell inpu ts and outputs. dedicated high-performance lines are c onnected as needed for fast, low-skew global signal distribution throughout the core. maximum core utilization is possible for virtually any design. proasic plus devices also contain embedded, two-port sram blocks with built-i n fifo/ram control logic. programming options include synchronous or asynchronous operation, two-port ram configurations, user-defined depth and width, and parity generation or checking. refer to the "embedded memory specifications" section on page 2-54 for more information. figure 1-1 ? the proasic plus device architecture figure 1-2 ? flash switch 256x9 two-port sram or fifo block logic tile 256x9 two port sram or fifo block ram block ram block i/os sensing switching switch in switch out w ord floating gate
proasic plus flash family fpgas v5.9 1-3 live at power-up the actel flash-based proasic plus devices support level 0 of the live at power-up (lapu) classification standard. this feature he lps in system component initialization, executing cr itical tasks before the processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. the lapu feature of flash-based proasic plus devices greatly simplifies total system design and reduces total system cost, often eliminat ing the need for complex programmable logic device (cpld) and clock generation plls that are used for th is purpose in a system. in addition, glitches and brow nouts in system power will not corrupt the proasic plus device's flash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when syst em power is restored. this enables the reduction or complete removal of the configuration prom, expe nsive voltage monitor, brownout detection, and clock generator devices from the pcb design. flash-based proasic plus devices simplify total system design, and reduce cost and design risk, while increasing system relia bility and improving system initialization time. flash switch unlike sram fpgas, proasic plus uses a live-at-power-up isp flash switch as it s programming element. in the proasic plus flash switch, two transistors share the floating gate, which stores the programming information. one is the sens ing transistor, which is only used for writing and verification of the floating gate voltage. the other is the sw itching transistor. it can be used in the architecture to connect/separate routing nets or to configure logic. it is also used to erase the floating gate ( figure 1-2 on page 1-2 ). logic tile the logic tile cell ( figure 1-3 ) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). any three-input, one-output logic function (except a three-input xor) can be configured as one tile. the tile can be conf igured as a latch with clear or set or as a flip-flop with clear or set. thus, the tiles can flexibly map logic and sequential gates of a design. figure 1-3 ? core logic tile local routing in 1 in 2 (clk) in 3 (reset) efficient long-line routing
proasic plus flash family fpgas 1-4 v5.9 data sheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definition of th ese categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advance this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. export administration regulations (ear) the products described in this datasheet are subject to th e export administration regu lations (ear). they could require an approved export license prior to export from th e united states. an export in cludes release of product or disclosure of technology to a foreign nati onal inside or outsid e the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advance status datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product intr oduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitness of any actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life- support, and other high-relia bility applications. con sult actel?s terms an d conditions for specif ic liability exclusions relating to life-support applic ations. a reliability report covering all of actel?s products is available on the actel website at http://www.actel.com/documents /ort_report.pdf. actel also offers a variety of enhanced qualification and lot acceptance screening procedures. c ontact your local actel sales office for additional reliability information.
5172161-25/12.09 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court, meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu building 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel is the leader in low-power and mixed-signal fp gas and offers the most comprehensive portfolio of system and power management solutions. po wer matters. learn more at www.actel.com.
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